Performance assessment and optimization of a thin-film thermoelectric cooler for on-chip transient thermal management. (April 2023)

• Record Type: Journal Article
• Authors: Gong, Tingrui; Li, Lianghui; Shi, Maolin; Kang, Lingfeng; Gao, Lei; Li, Juntao
• Is Part Of: Applied thermal engineering. Volume 224(2023)
• Publication Date: 2023-04
• Subjects: Thin-film thermoelectric cooler -- 3D electronic package -- On-chip transient thermal management -- Multi-objective optimization -- Response surface method; Heat engineering -- Periodicals; Heating -- Equipment and supplies -- Periodicals; Periodicals; 621.40205
• DOI: 10.1016/j.applthermaleng.2023.120079
• Languages: English
• ISSNs: 1359-4311

Abstract

Highlights: A system-level transient optimization of TFTEC for on-chip cooling is performed. Response surface method is applied to obtain performance predictive models. Single- and multi-objective optimizations are used to optimize the system. TFTEC-assisted on-chip cooling system enables considerable hotspot cooling. TFTEC allows the chip to sustain high-power pulses for longer periods of time. Abstract: On-demand cooling of thin-film thermoelectric cooler (TFTEC) is a promising technique for energy-saving and high efficiency. However, the transient cooling process of TFTEC is complex and systematic, involving temperature-dependent material properties, geometry factors, parasitic parameters and control parameters. In this work, a system-level optimization of the on-chip transient thermal management (TTM) performance of a Bi2 Te3 -based TFTEC is performed using a transient three-dimensional numerical model. The response surface method is applied to obtain a predictive model for evaluating the transient cooling performance of TFTEC in terms of four different design factors of thermoelectric leg height, electrode height, current pulse width and amplitude. The relationships between the above design factors and responses including passive cooling, active cooling, temperature overshoot, and time delay and their interactive effects are investigated. Finally, single- and multi-objective optimizations are employed to optimize these responses in different scenarios. The results show that the TFTEC with the optimal configuration enables a passive cooling of 15.57 °C and an active cooling of 5.85 °C simultaneously for a chip hotspot with a transient heat flux of 1300 W/cm 2 . Furthermore, the hotspot temperature can be limited to 7.15℃ lower than the predefined temperature limit, while the high-power pulse loading time can be extended by 690.2 ms.