3D layout of the Spidergon-Donut on-chip interconnection network. (6th April 2023)

• Record Type: Journal Article
• Authors: Sibai, Fadi N.; Asaduzzaman, Abu; Elmoursy, Ali
• Is Part Of: International journal of high performance systems architecture. Volume 11:Number 3(2023)
• Page Start: 137
• Page End: 147
• Publication Date: 2023-04-06
• Subjects: 3D integration -- 3D on-chip networks -- Spidergon-Donut network -- many-core processors -- wire delay -- chip area -- heat dissipation; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

3D integration promises to resolve many of the heat and die size limitations of 2D integrated circuits. A critical step in the design of 3D many-cores and MPSOCs is the layout of their 3D network-on-chip (NoC). In this paper, we explore and present multiple 3D layouts of the Spidergon-Donut (SD) NoC and estimate their longest wire lengths and cost requirements. For a total of 64 cores, the 4×2×8 and 2×4×8 placements result in the best longest wire delays, with the former higher 3D integration costs, while the second requiring larger chip area and through-silicon-vias (TSV) array costs. Such study helps in guiding 3D integration direction and weighing 3D NoC layout and placement alternatives.