High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit. (3rd April 2023)

• Record Type: Journal Article
• Authors: Singh, S.K. Binu Siva; Karthikeyan, K.V.
• Is Part Of: International journal of high performance systems architecture. Volume 11:Number 3(2023)
• Page Start: 148
• Page End: 155
• Publication Date: 2023-04-03
• Subjects: DPWM -- digital pulse width modulator -- decoder -- synchronous reversible counter -- synchronous phase shifted circuit -- reversible synchronous sequential counter -- D-flip flop -- delay line output duty cycle -- linearity -- time resolution; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE.