A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm. Issue 2 (22nd February 2021)
- Record Type:
- Journal Article
- Title:
- A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm. Issue 2 (22nd February 2021)
- Main Title:
- A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm
- Authors:
- Mariappan, Selvakumar
Rajendran, Jagadheswaran
Mohd Noh, Norlaili
Yusof, Yusman
Kumar, Narendra - Abstract:
- Abstract : Purpose: The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach: The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3 ) to be canceled with the main PA's fixed negative gm3 . The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings: For driver's VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value: In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.
- Is Part Of:
- Circuit world. Volume 48:Issue 2(2022)
- Journal:
- Circuit world
- Issue:
- Volume 48:Issue 2(2022)
- Issue Display:
- Volume 48, Issue 2 (2022)
- Year:
- 2022
- Volume:
- 48
- Issue:
- 2
- Issue Sort Value:
- 2022-0048-0002-0000
- Page Start:
- 215
- Page End:
- 222
- Publication Date:
- 2021-02-22
- Subjects:
- CMOS -- Long term evolution -- Power added efficiency -- Power amplifier
Electronic circuits -- Design and construction -- Periodicals
Electronic circuits -- Periodicals
621.381505 - Journal URLs:
- http://firstsearch.oclc.org ↗
http://www.emeraldinsight.com/0305-6120.htm ↗
http://www.emeraldinsight.com/cw.htm ↗
http://www.emeraldinsight.com/journals.htm?issn=0305-6120 ↗
http://www.emeraldinsight.com/ ↗ - DOI:
- 10.1108/CW-08-2020-0209 ↗
- Languages:
- English
- ISSNs:
- 0305-6120
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 3198.839000
British Library DSC - BLDSS-3PM
British Library STI - ELD Digital store - Ingest File:
- 25887.xml