Silicon circuits for chip‐to‐chip communications in multi‐socket server board interconnects. Issue 2 (22nd March 2021)

• Record Type: Journal Article
• Authors: Moralis‐Pegios, Miltiadis; Pitris, Stelios; Mitsolidou, Charoula; Fotiadis, Konstantinos; Ramon, Hannes; Lambrecht, Joris; Bauwelinck, Johan; Yin, Xin; Ban, Yoojin; De Heyn, Peter; Van Campenhout, Joris; Lamprecht, Tobias; Lehnman, Andreas; Pleros, Nikos; Alexoudi, Theoni
• Other Names: Pleros Nikos guestEditor.; Melloni Andrea guestEditor.; Alexoudi Theonitsa guestEditor.
• Is Part Of: IET optoelectronics. Volume 15:Issue 2(2021)
• Page Start: 102
• Page End: 110
• Publication Date: 2021-03-22
• Subjects: Optoelectronics -- Periodicals; 621.36
• DOI: 10.1049/ote2.12018
• Languages: English
• ISSNs: 1751-8768

Abstract

Abstract: Multi‐socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with the interconnect technology comprising a key element in boosting processing performance. Here, we present an overview of the current electrical interconnects for MSBs, outlining the main challenges currently faced. We propose the use of silicon photonics (SiPho) towards advancing interconnect throughput, socket connectivity and energy efficiency in MSB layouts, enabling a flat‐topology wavelength division multiplexing (WDM)‐based point‐to‐point (p2p) optical MSB interconnect scheme. We demonstrate WDM SiPho transceivers (TxRxs) co‐assembled with their electronic circuits for up to 50 Gb/s line rate and 400 Gb/s aggregate data transmission and SiPho arrayed waveguide grating routers that can offer collision‐less time of flight connectivity for up to 16 nodes. The capacity can scale to 2.8 Gb/s for an eight‐socket MSB, when line rate scales to 50 Gb/s, yielding up to 69% energy reduction compared with the QuickPath Interconnect and highlighting the feasibility of single‐hop p2p interconnects in MSB systems with >4 sockets.