An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms. (15th February 2021)

• Record Type: Journal Article
• Authors: Shimozato, Kyohei; Nakamura, Yohei; Bian, Song; Sato, Takashi
• Is Part Of: Japanese journal of applied physics. Volume 60:Number SB(2021)
• Publication Date: 2021-02-15
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.35848/1347-4065/abdc5c
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.