Device and circuit-level evaluation of a zero-cost transistor architecture developed via process optimization. (March 2023) - Devoge, Paul; Aziza, Hassen; Lorenzini, Philippe; Masson, Pascal; Malherbe, Alexandre; Julien, Franck; Marzaki, Abderrezak; Regnier, Arnaud; Niel, Stephan
Highlights: Ring oscillator are used to evaluate the performance of a new zero-cost transistor. A reliability evaluation is done at the device level and at the circuit level. Higher frequency is measured for the new device, especially when load capacitors are added. Abstract: In this work, ring oscillator test structures are designed and characterized to evaluate the in-circuit performance of a new medium-voltage (around 2–5 V) transistor architecture developed via process optimization in a 40 nm embedded non-volatile memory (eNVM) CMOS technology. The transistor is zero-cost in terms of photomask and process steps. It is compared to an existing transistor available in the technology. A SPICE model (Simulation Program with Integrated Circuit Emphasis) of the new device is developed to evaluate its circuit-level performance through electrical simulations. The simulation results are complemented by experimental results, and both show a large increase in the ring oscillator frequency for the new transistor, compared to the existing one. In addition, the reliability of the new transistor is evaluated at the device level with hot-carrier injection (HCI) stress tests and at the circuit level with power-supply stress tests.