Investigation and validation of PV fed reduced switch asymmetric multilevel inverter using optimization based selective harmonic elimination technique. (3rd July 2023)

• Record Type: Journal Article
• Authors: Jayakumar, T.; Ramani, G.; Jamuna, P.; Ramraj, B.; Chandrasekaran, Gokul; Maheswari, C.; Stonier, Albert Alexander; Peter, Geno; Ganji, Vivekananda
• Is Part Of: Automatika. Volume 64:Number 3(2023)
• Page Start: 441
• Page End: 452
• Publication Date: 2023-07-03
• Subjects: Multilevel inverter -- SEPIC converter -- selective harmonics elimination -- MPPT algorithm -- GWO algorithm -- multi carrier -- DSPIC controller; Automatic control -- Periodicals; 629.805
• DOI: 10.1080/00051144.2023.2173121
• Languages: English
• ISSNs: 0005-1144

Abstract

Abstract : Pulse width modulation for Selective Harmonics Elimination (SHE) is mostly employed in the reduction of lower order harmonics. The PV system in this research provides input voltage to the reduced switch 31-level inverter, which is based on the Artificial Bee Colony algorithm. With a high gain DC-DC single-ended primary-inductor converter (SEPIC), the PV panel output voltage is kept constant. The Grey wolf optimization algorithm (GWO) approach is used to get the most power out PV scheme. Multi Carrier modulation, a high-frequency modulation technology, is also used in this novel design of the inverter to reduce upper order harmonics. The suggested Artificial Bee Colony (ABC) algorithm, harmonics is compared to a SHE technique based on a genetic algorithm. The hardware findings were confirmed using DSPIC30F2010 controller simulation, and the recommended system was validated using Matlab simulation.