A low noise 2.2 GHz PLL ASIC for the CSR external-target experiment. (1st February 2023) - Hu, Z.; Gao, C.; Tian, X.; Zhu, P.; Liu, J.; Wang, H.; Chen, K.; You, B.; Xiao, L.; Guo, D.; Yang, P.; Qiao, Y.; et al.
Abstract: This paper presents the design and test results of a low noise Phase Locked Loop (PLL) Application Specific Integrated Circuit (ASIC), which is designed for the data transmission system in a pixel chip for a beam monitor of the Cooling Storage Ring (CSR) external target experiment at HIRFL in China. The proposed PLL consists of a differential ring oscillator, a digital divider, a three-state phase frequency detector, a current charge pump, a second-order loop filter and current mode level buffers. A prototype PLL ASIC has been fabricated in a standard 130 nm CMOS process. The test results show that the frequency of the output clock is about 2.2 GHz with a phase noise of −90 dBc/Hz at a frequency offset of 1 MHz and a root mean square jitter of 1.15 ps. The core circuit of the PLL consumes about 30 mW under the power supply of 1.2 V.