An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheads. Issue 12 (8th September 2022)

• Record Type: Journal Article
• Authors: Kumar, Sudhakar; Singh, Sunil K.; Aggarwal, Naveen; Gupta, Brij B.; Alhalabi, Wadee; Band, Shahab S.
• Is Part Of: International journal of intelligent systems. Volume 37:Issue 12(2022)
• Page Start: 11764
• Page End: 11790
• Publication Date: 2022-09-08
• Subjects: automatic parallelization -- batchwise transaction -- hardware transactional memory -- intelligent system -- LLVM compiler infrastructure -- speculative parallelization; Artificial intelligence -- Periodicals; Expert systems (Computer science) -- Periodicals; Intelligence artificielle -- Périodiques; Systèmes experts (Informatique) -- Périodiques; 006.3
• DOI: 10.1002/int.23062
• Languages: English
• ISSNs: 0884-8173

Abstract

Abstract: In the last few decades, technology advancements have paved the way for the creation of intelligent and autonomous systems that utilize complex calculations which are both time‐consuming and central processing unit intensive. As a consequence, parallel processing systems are gaining popularity to enhance overall computer performance. Programmers should be able to efficiently utilize available hardware resources with parallelization in an ideal world. Through the automatic parallelization of sequential code, multithreading can be executed without extra supervision. However, a wide range of software dependencies prevents this from being feasible. An architectural framework for speculative parallelization along with an efficient memory analysis and computational algorithms for the code generation are proposed that can provide optimal performance. Furthermore, a suitable support of hardware design as a runtime library to the proposed architectural framework is presented which can be used to recover misspeculated results during execution to minimize speculative parallelism overhead. The implementation makes use of the Low‐Level Virtual Machine compiler infrastructure and is tested on numerous benchmarks, thus making it highly scalable in terms of programming languages and architectures. According to our experimental results, there is significant potential for speedup increase. In comparison to the overall function speedup, that is, geomean speedup of 5.2× approximately when using the proposed architecture without hardware support, the proposed architectural framework and algorithm with hardware support give an average geomean speedup of 7.0× approximately on the given benchmark which is written in C/C++.