Fabrication of 3-Layer Stacked Pixel for Pixel-Parallel CMOS Image Sensors by Au/SiO2 Hybrid Bonding of SOI Wafers. (8th September 2020)

• Record Type: Journal Article
• Authors: Goto, Masahide; Nakatani, Naoki; Honda, Yuki; Watabe, Toshihisa; Nanba, Masakazu; Iguchi, Yoshinori; Saraya, Takuya; Kobayashi, Masaharu; Higurashi, Eiji; Toshiyoshi, Hiroshi; Hiramoto, Toshiro
• Is Part Of: ECS transactions. Volume 98:Number 4(2020)
• Page Start: 167
• Page End: 171
• Publication Date: 2020-09-08
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/09804.0167ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We report 3-layer stacked image sensor pixel designed for pixel-parallel complementary metal-oxide-semiconductor (CMOS) image sensors. Direct bonding of silicon-on-insulator (SOI) wafers with Au electrodes embedded in a SiO2 surface achieves high-density pixel-wise interconnection. By applying the bonding, backside electrode forming, and handle layer removing processes, we have obtained 3-layer stacked wafer without voids or separations. Measurement of prototype 3-layered pixel confirmed linear response of 16-bit digital signal output, demonstrating feasibility of multi-layer devices with functional diversification including circuits, sensors, and More-than-Moore type devices.