Analysis and implementation of SDH protocol in 10Gbps POS signal. (September 2020)

• Record Type: Journal Article
• Authors: Wei, Ying; Huang, Jiawei; Ling, Liuyi
• Is Part Of: Journal of physics. Volume 1633(2020)
• Publication Date: 2020-09
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/1633/1/012089
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: The data transmission network based on synchronous digital Hierarchy (SDH) can fundamentally solve the problems of capacity, quality, network management, security and so on in the network transmission of IP services. POS (Packet Over SDH) technology is a way to implement IP service in SDH data transmission network. An analytical solution of SDH protocol with Stratix5 FPGA as the core is studied. According to the SDH standard defined by ITU-T, the analytical circuit of SDH protocol in 10Gbps POS signal is designed on FPGA. The circuit is divided into data receiving module, line overhead module, channel spending module and status register output module, to complete data receiving, information extraction, and output of state information and net load data. The results of functional simulation and board level test show that the scheme is accurate, efficient and consistent with the standard, which can provide some reference value for the development of SDH technology.