Reduced Instruction Set Computer (RISC): A Survey. Issue 1 (May 2021)

• Record Type: Journal Article
• Authors: Bansal, Malti; Harsh,
• Is Part Of: Journal of physics. Volume 1916:Issue 1(2021)
• Publication Date: 2021-05
• Subjects: RISC -- MIPS -- ARM -- Clock Gating -- Wallace Tree Multiplier -- ALU; Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/1916/1/012040
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: Today's modern machines are designed to process real time problems and to do so designers try to make them more performance efficient but while doing this, the complexity of design also increases. So, to maintain a balance between both we have to manage this complexity. Now, a question arises how can we do this? The answer resides in our own life. For instance, when we have a complex task to do, we often break it down into simpler sub-tasks and then work upon them individually. How well we are able to do this depends upon the efficiency of our brain. Same analogy we can apply to design processor architecture. To further improve the efficiency, RISC methodology can be proven to be a prominent choice. The RISC is a design methodology which plays an important part in modern embedded systems. From our day-to-day applications like mobile phones to some of the world's fastest supercomputers like FUGAKU, all are based on RISC architecture. With the advancements in the scaling field and reduction in the price of the ICs, the market starts filling with the RISC based processor. This paper is focused on providing a basic idea about RISC Architecture based processor design and laying out a path that one can follow to design their own RISC processor. Also, Power outages in ICs are the major problem in the VLSI industry so various techniques and methods are also discussed that can be used for optimizing power and improving speed. Some of the major applications are also discussed which provide an idea about the extent of applications, RISC based architecture can be designed.