Design and application of digital phase locked loop based on Quartus II. Issue 1 (December 2020)

• Record Type: Journal Article
• Authors: Xie, Yan; Zhou, Jin; Kang, Shengwu
• Is Part Of: IOP conference series. Volume 617:Issue 1(2020)
• Publication Date: 2020-12
• Subjects: Earth sciences -- Periodicals; Environmental sciences -- Congresses; Environmental sciences -- Periodicals; 550.5
• DOI: 10.1088/1755-1315/617/1/012026
• Languages: English
• ISSNs: 1755-1307

Abstract

Abstract: The traditional phase locked loop (PLL) is realized by analog circuit. Compared with PLL realized by traditional analog circuit, digital phase locked loop (DPLL) has the advantages of high precision, not affected by temperature and voltage, adjustable loop bandwidth and center frequency, and easy to construct high-order PLL. With the rapid development of communication technology and integrated circuit technology, DPLL will be more widely used. In this paper, the PLL macroblock is used to design and realize the functions of frequency division, frequency doubling and phase locking in Quartus II development environment. The validity of the design and application of the DPLL is verified by practical verification.