Wet Processing for Post-epi & Pre-furnace Cleans in Silicon Carbide Power MOSFET Fabrication. (11th September 2015)

• Record Type: Journal Article
• Authors: McMahon, J. Jay; Jahanbani, Mo; Arthur, Stephen; Lilienfeld, David; Gipp, Pete; Gorczyca, Thomas; Formica, J.; Shen, L.; Yamagami, M.; Hillard, Bob; Byrnes, John
• Is Part Of: ECS transactions. Volume 69:Number 8(2015)
• Page Start: 269
• Page End: 276
• Publication Date: 2015-09-11
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/06908.0269ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Silicon carbide (SiC) device fabrication technology shares many similarities with Si manufacturing, but identifying whether material differences affect cleaning capability is of interest for this growing field. Material parameter differences include diffusion coefficients, surface energy, and chemical bond strength, all of which can play a role in cleaning critical surfaces. This work compares trace surface contamination levels (as measured by TXRF) after 100 mm or 150 mm 4H SiC wafers underwent mercury-probe capacitance voltage (MCV) mapping, to levels after subsequent cleans. Trace levels of metals such as Hg, Fe, and Ni were controllably added during MCV, and it was shown that a variety of cleaning approaches can return the SiC surface to sub-5x10 10 atoms/cm 2 levels of cleanliness. Where these cleans fit into an integrated device process flow and comparison of cost are discussed.