A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor. Issue 4 (4th July 2017)

• Record Type: Journal Article
• Authors: Chaudhary, Tarun; Khanna, Gargi
• Is Part Of: IETE journal of research. Volume 63:Issue 4(2017)
• Page Start: 451
• Page End: 460
• Publication Date: 2017-07-04
• Subjects: 2D analytical model -- Central potential -- Dielectric thickness -- JL SDG VeSFET -- Scaling -- Surface potential -- Threshold voltage -- Vth roll-off -- Work function; Electronics -- Periodicals; Telecommunication -- Periodicals; Electronics; Telecommunication; Periodicals; 621.38
• DOI: 10.1080/03772063.2017.1292154
• Languages: English
• ISSNs: 0377-2063

Abstract

ABSTRACT: In the present paper, a two-dimensional (2D) potential-based analytical model of threshold voltage for junctionless symmetric double gate vertical slit field effect transistor (JL SDG VeSFET) is developed. The proposed model is based upon the solution of 2D Poisson's equation and is also extended to consider the effect of third dimension on threshold voltage of the device. The model includes the effect of various device parameters such as geometric gate length, dielectric thickness, substrate doping, and metal gate work function on threshold voltage, and is compared with conventional metal oxide semiconductor field effect transistor (MOSFET) device in order to show better performance of junctionless transistor and its application for future low power very large scale integration (VLSI) circuits. The analytical model is assessed with 2D TCAD Sentaurus simulation. The analytical model not only provides useful physical insight into the subthreshold behavior of the device, but also offers basic design guideline to better exploit its scaling potential for future nanoscale devices. It has been reported that the proposed model is in good agreement with simulative analysis with only a marginal deviation of about 3% for various device parameters.