Design and error-rate evaluation of RSFQ logic gates comprising a toggle storage loop. (July 2020)

• Record Type: Journal Article
• Authors: Yamazaki, Koki; Shimada, Hiroshi; Mizugaki, Yoshinao
• Is Part Of: Journal of physics. Volume 1590(2020)
• Publication Date: 2020-07
• Subjects: Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/1590/1/012042
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: We propose an RSFQ digital cell with a toggle storage loop structure for logical NOT operation. Logical NOT operation is a fundamental function of digital circuitry, and hence, it had better be realized with less devices. We demonstrate a simpler and area-halved NOT gate designed as a 40 x 80 μm 2 cell, which follows to cell-based design methodology. Test circuits were fabricated using a 2.5kA/cm 2 Nb integration process. Measurements were executed in a liquid helium bath. We confirmed that the NOT gate comprising a toggle storage loop worked correctly. The error-rate of the NOT gate was less than 8.33 x 10 −6 in the bias voltage range from 2.111 to 3.165 mV, which corresponded to the bias margin from 84.4% to 126.6% of the nominal bias voltage (2.5 mV). We also present that NOR and NAND logic gates can be configured using a toggle storage loop.