Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA. Issue 1 (18th February 2021)

• Record Type: Journal Article
• Authors: Mohan Kumar, B.N.; Rangaraju, H.G.
• Is Part Of: International journal of intelligent unmanned systems. Volume 10:Issue 1(2022)
• Page Start: 145
• Page End: 158
• Publication Date: 2021-02-18
• Subjects: Finite impulse response -- Moore based loopback adder -- Processing element -- Vedic multiplier -- CSLA adder; Vehicles, Remotely piloted -- Periodicals; Robots -- Control systems -- Periodicals; Mechanical engineering -- Robots -- Periodicals; Robotics -- Periodicals; Submersibles -- Periodicals; Space vehicles -- Command control systems -- Periodicals; 629.046
• DOI: 10.1108/IJIUS-09-2020-0056
• Languages: English
• ISSNs: 2049-6427

Abstract

Abstract : Purpose: Finite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs. Design/methodology/approach: To overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices. Findings: The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter. Originality/value: The experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.