A Spatial ALD Oxide Passivation Module in an All-Spatial Etch-Passivation Cluster Concept. (10th September 2015)

• Record Type: Journal Article
• Authors: Roozeboom, Fred; van den Bruele, Fieke; Creyghton, Yves; Poodt, Paul; Kessels, W.M.M.
• Is Part Of: ECS transactions. Volume 69:Number 7(2015)
• Page Start: 243
• Page End: 258
• Publication Date: 2015-09-10
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/06907.0243ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : Traditional plasma etching in silicon is often based on the so-called 'Bosch' etch with alternating half-cycles of a directional Si-etch and a fluorocarbon polymer passivation, respectively. Also shallow feature etching is often performed as a cycled process. Similarly, ALD is cyclic with the additional benefit of being composed of half-reactions that are self-limiting, thus enabling a layer-by-layer growth mode. To accelerate growth rate, spatial ALD has been commercialized as a large-scale, high-throughput, atmospheric-pressure method. In this paper we describe a related concept for high-rate spatially-divided etching which eventually may be further developed towards Atomic Layer Etching. The process is converted from the time-separated into the spatially-separated regime by inserting N2 -gas 'curtains' confining the reactive gases to individual injection slots in a gas injector head, and also serving as gas-bearing. By moving substrates back and forth under such gas injector one can perform alternate etching/passivation-deposition cycles at optimized local pressures, thus eliminating the idle times for switching pressure or purging. An extra improvement towards an all-spatial approach is the use of ALD-based oxide (Al2 O3, SiO2, etc.) as passivation during, or as gap-fill after etching. This disruptive concept, named spatial ALD-enabled RIE, has industrial potential for cost-effective front-end-of-line and back-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Besides in CMOS scaling this etch concept may also become an interesting option for fast die dicing of silicon (or III/V) in TSV and MEMS processing.