(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies. (16th August 2017)

• Record Type: Journal Article
• Authors: He, Xiaoli; Triyoso, Dina; Uppal, Suresh; Fu, Bianzhu; Zhang, Xing; Yamaguchi, Shimpei; Yong, Chloe; Liu, Bingwu; Joshi, Manoj; Samavedam, Srikanth
• Is Part Of: ECS transactions. Volume 80:Number 1(2017)
• Page Start: 373
• Page End: 378
• Publication Date: 2017-08-16
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/08001.0373ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : In FinFET technology, device threshold voltage (Vt ) stability is a pre-requisite for volume manufacturing. Device architectural elements, process parameters and room temperature aging (Q-time) are the main source of Vt instability. For the first time, we report a method to minimize Vt instability due to Q-time in gate stack work function (n-WF) layer film depositions. Underlying mechanism was investigated using elemental analysis. The optimized n-WF layer recipes were developed that are less sensitive to the Q-time. Device benefits such as Tinv scaling and thereby Ion -Ioff performance improvement is demonstrated without compromising the reliability.