Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks. Issue 1 (10th August 2021)

• Record Type: Journal Article
• Authors: Kumar, B.N. Mohan; Rangaraju, H.G.
• Is Part Of: International journal of pervasive computing and communications. Volume 18:Issue 1(2022)
• Page Start: 43
• Page End: 58
• Publication Date: 2021-08-10
• Subjects: SDR -- Equalizer -- Parallel prefix adder -- DA-based multiplier -- FIR filter design -- Modified distributed arithmetic -- LUT-based multiplier -- FIR -- FPGA -- Reconfigurable architecture -- VLSI; Ubiquitous computing -- Periodicals; Mobile computing -- Periodicals; Computer network protocols -- Periodicals; Computer network architectures -- Periodicals; Application software -- Development -- Periodicals; 004.6
• DOI: 10.1108/IJPCC-04-2021-0086
• Languages: English
• ISSNs: 1742-7371

Abstract

Abstract : Purpose: Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach: The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings: The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value: The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.