Experiment Design Regularization-Based Hardware/Software Codesign for Real-Time Enhanced Imaging in Uncertain Remote Sensing Environment. (9th March 2010)

• Record Type: Journal Article
• Authors: Castillo Atoche Castillo Atoche, A. A.; Torres Roman Torres Roman, D. D.; Shkvarko Shkvarko, Y. Y.
• Other Names: Wess Wess Bernhard Bernhard Academic Editor.
• Is Part Of: EURASIP journal on advances in signal processing. Volume 2010(2010)
• Publication Date: 2010-03-09
• Subjects: Signal processing -- Periodicals; Traitement du signal; Signal processing; Periodicals; 621.3822
• DOI: 10.1155/2010/254040
• Languages: English
• ISSNs: 1687-6172

Abstract

Abstract : A new aggregated Hardware/Software (HW/SW) codesign approach to optimization of the digital signal processing techniques for enhanced imaging with real-world uncertain remote sensing (RS) data based on the concept of descriptive experiment design regularization (DEDR) is addressed. We consider the applications of the developed approach to typical single-look synthetic aperture radar (SAR) imaging systems operating in the real-world uncertain RS scenarios. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale SAR image enhancement tasks. The innovative algorithmic idea is to incorporate into the DEDR-optimized fixed-point iterative reconstruction/enhancement procedure the convex convergence enforcement regularization via constructing the proper multilevel projections onto convex sets (POCS) in the solution domain. The hardware design is performed via systolic array computing based on a Xilinx Field Programmable Gate Array (FPGA) XC4VSX35-10ff668 and is aimed at implementing the unified DEDR-POCS image enhancement/reconstruction procedures in a computationally efficient multi-level parallel fashion that meets the (near) real-time image processing requirements. Finally, we comment on the simulation results indicative of the significantly increased performance efficiency both in resolution enhancement and in computational complexity reduction metrics gained with the proposed aggregated HW/SW co-design approach.