Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. (20th February 2011)

• Record Type: Journal Article
• Authors: Le Gal Le Gal, Bertrand Bertrand; Casseau Casseau, Emmanuel Emmanuel
• Other Names: López López Juan A. Juan A. Academic Editor.
• Is Part Of: EURASIP journal on advances in signal processing. Volume 2011(2011)
• Publication Date: 2011-02-20
• Subjects: Signal processing -- Periodicals; Traitement du signal; Signal processing; Periodicals; 621.3822
• DOI: 10.1155/2011/927670
• Languages: English
• ISSNs: 1687-6172

Abstract

Abstract : High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on uniform-width resources according to the worst-case data requirements, that is, the largest word length. HLS techniques have been reviewed for the last few years to benefit from multiple word-length fixed point description of the algorithms to be implemented. Aims were to save design area and power consumption. Unfortunately, data-width timing issues over the operation's latency have not been taken into account accurately. In this paper, an HLS process that takes care of the delay of the operators according to the data width is presented. Experimental results show that our approach achieves significant design latency saving or area decrease compared to a conventional synthesis.