A 10‐GHz bandwidth 45.5‐dB SNDR buffer with local feedback in 45‐nm CMOS. Issue 2 (14th January 2023)

• Record Type: Journal Article
• Authors: Wu, Jie; Meng, Qiao; Li, Fei; Huang, Yujia
• Is Part Of: Electronics letters. Volume 59:Issue 2(2023)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2023-01-14
• Subjects: buffer circuits -- circuits -- CMOS analogue integrated -- feedback -- high‐speed integrated circuits; Electronics -- Periodicals; 621.381
• DOI: 10.1049/ell2.12710
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract: A high‐speed and low‐power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high‐speed circuits operating at 20 GS/s. This novel two‐stage buffer is employed with bandwidth expansion and slew‐rate enhanced techniques. An improved common‐mode feedback circuit stabilizes the output common‐mode voltage. This prototype buffer is fabricated in the 45‐nm COMS process, and achieves 7.2 bit ENOB at 10‐GHz input frequency with power consumption of 20.4 mW, load of 0.3 fF. Abstract : This article proposes a novel local feedback buffer which can be used in driving interleaving circuit. The buffer utilizes peaking and slew‐rate enhancement techniques to achieve high speed.