Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node. (1st January 2023)

• Record Type: Journal Article
• Authors: Valasa, Sresta; Ramakrishna, K. V.; Vadthiya, Narendar; Bhukya, Sunitha; Rao, N. Bheema; Maheshwaram, Satish
• Is Part Of: ECS journal of solid state science and technology. Volume 12:Number 1(2023)
• Publication Date: 2023-01-01
• Subjects: Solid state chemistry -- Periodicals; Electronics -- Materials -- Periodicals; Electrochemistry -- Periodicals; 541.0421
• DOI: 10.1149/2162-8777/acb175
• Languages: English
• ISSNs: 2162-8777

Abstract

Abstract : This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction ( ∅ m ) and fin thickness (Tfin ) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in ∅ m and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP ) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm ), intrinsic gain (AV ), transconductance generation factor (TGF), cutoff frequency (fT ), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP ) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.