Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver. (1st January 2023) - Bandi, F.; Ballabriga, R.; Borghello, G.; Campbell, M.; Caratelli, A.; Ceresa, D.; Hofmann, T.; Kaplon, J.; Kloukinas, K.; Michelis, S.; Pejašinović, R.; Piernas-Díaz, F.; et al.
Abstract: A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitter's output is powered with 1.2 V to provide compatibility with previous designs, while the core logic can be powered with 0.8 V to reduce power consumption. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in High Energy Physics will be discussed along with characterization results. Other IP blocks are being designed (ADC, DAC, PLL) and they will be presented.