A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA micro-vertex detector. (1st January 2023) - Mazza, G.; Calvo, D.; Cossio, F.; De Remigis, P.; Mignone, M.; Wheadon, R.; Silvestrin, L.; Tessaro, M.; ,
Abstract: The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the double-sided silicon strip sensors that will equip the micro-vertex detector of the PANDA experiment. The ToASt ASIC operates with a 160 MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.