A greedy algorithm based Compensation Circuit for Optimizing the Output Statistics of APUF. (January 2023)

• Record Type: Journal Article
• Authors: Lian, Jiana; Wang, Pengjun; Li, Gang
• Is Part Of: Microelectronics journal. Volume 131(2023)
• Publication Date: 2023-01
• Subjects: Physical unclonable function -- Greedy algorithm -- Differential compensation -- Field-programmable gate array; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105636
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Physical unclonable function (PUF) can reduce the risk of password leakage of smart connected devices, and has broad application prospects in the field of information security. However, in actual implementation, the designed PUF often deviates greatly due to a lack of experience in using the FPGA platform. Therefore, this paper proposes an APUF adaptive compensation method based on a greedy algorithm. This method can modify the delay by changing the internal transmission path, thereby reducing the skew between APUF paths. First, to enhance the randomness of the APUF output, a compensation circuit with equal delay on the symmetric path of APUF is constructed in a differential manner. Then, the local solution is used to construct the global solution by using the greedy algorithm, which further improves the circuit regulation speed. Finally, the proposed method is implemented on FPGA, and the effectiveness of the method is verified by analyzing the statistical characteristics of the output. The experimental results show that the randomness (49.56%), uniqueness (49.08%), and reliability (95.78%) of APUF are close to the ideal values after using the adaptive compensation method. In addition, when implemented on different FPGA platforms and different chip locations, the average randomness of the PUF circuit is 49.46%. Therefore, the method is highly applicable and can be applied to all the same types of FPGA platforms without subsequent adjustments.