A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter. (January 2023)

• Record Type: Journal Article
• Authors: Jin, Wei; Pun, Kong-Pang
• Is Part Of: Microelectronics journal. Volume 131(2023)
• Publication Date: 2023-01
• Subjects: Delta–sigma modulator -- Continuous time -- Power-efficient -- Calibration-free -- Switched capacitor -- Multi-level DAC -- Low-pass filter -- Hybrid loop; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105666
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This article demonstrates the circuit technique of a highly power-efficient continuous-time (CT) Delta–sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF). The technique addresses the clock sensitivity issue of conventional DACs while maintaining the alias rejection. It is validated by a fourth-order CT DSM prototype fabricated in 65-nm CMOS technology. The input stage of the DSM is an active-RC integrator merged with a passive front-end LPF. A resonator follows and realizes the cascade of resonators with feedforward (CRFF) structure. The accurate feedback loop employs a highly linear and calibration-free 5-level SC DAC. Based on the linear periodically time-varying (LPTV) system model, an exact analysis is given to explain the effects of the passive LPF and SC DAC combo on the signal transfer function (STF), and hence, on the alias rejection. The prototype DSM achieves a 70.2-dB signal to noise and distortion ratio (SNDR) and an 85.1-dB spurious-free dynamic range (SFDR) in a 10-MHz bandwidth, while dissipating 1.1 mW with a 1-V supply. The modulator achieves a 65.4-dB alias rejection and confirms the closed-form analytical results.