Adaptive parallel tiled code generation and accelerated auto-tuning. (November 2013)

• Record Type: Journal Article
• Authors: Tavarageri, Sanket; Ramanujam, J; Sadayappan, P
• Is Part Of: International journal of high performance computing applications. Volume 27:Number 4(2013)
• Page Start: 412
• Page End: 425
• Publication Date: 2013-11
• Subjects: parallel parametric tiling -- dynamic tile size adaptation -- accelerated auto-tuning -- code generation -- tile size selection; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342013493939
• Languages: English
• ISSNs: 1094-3420

Abstract

Tiling is an important program transformation that is often used to enhance cache locality and to obtain coarse-grained parallelism. In this paper, we address the problem of generating adaptive parametric tiled code for parallel execution contexts; in other words, generating parallel tiled code in which tile sizes can be changed on the fly during execution. Changing of tile sizes during pipelined parallel execution of tiles presents the following fundamental code-generation challenge: the unscanned iteration space may become non-convex. We develop novel solutions for the adaptive parallel tiled code generation problem. Using adaptive tiling, auto-tuning for tile size selection can be accelerated: in a single run of the tiled code, several tile sizes may be tested for their performance and thus expedite auto-tuning. Adaptive tiling is also useful in scenarios where tile sizes need to be dynamically altered to tailor to the changing execution environments, such as dynamically resized caches for power savings. Experimental evaluation on a number of benchmarks demonstrates the effectiveness of the developed approach.