A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS. (February 2023) - Jin, Zirui; Hu, Ang; Shan, Xiaoyu; Zhang, Chengcheng; Cui, Jinsong; Lei, Jianming; Liu, Dongsheng
Abstract: This article proposes a fractional- N charge pump phase-locked loop ( C P-PLL) with fast two-point modulation calibration using Duty-Cycle and Polarity Tracking technique. The proposed calibration method can perform delay and gain calibration within 15 μs, respectively. A DTC-assisted Polarity Detector is used to track and countervail the propagation delay of two modulation paths. A TDC-based Duty-Cycle Detector is used to monitor and compensate the two paths gain mismatch. By comparing the code with the threshold set in the look-up table (LUT), a quick calibration can be achieved. To maintain high out-band phase noise performance and stronger robustness, a Class-C oscillator using Capacitance Desensitization technique and Cross-Bias technique is adopted in the design. The proposed C P-PLL is implemented in a standard 110-nm CMOS technology, occupying 2.7 mm 2 silicon area. The post-simulation results show the proposed calibration method can calibrate the delay/gain mismatch within 30 μs. Fast calibration mode supports calibration time within 62.5 ns. The phase noise performance is −91-dBc/Hz@100 kHz, −119-dBc/Hz@1 MHz. The entire C P-PLL dissipates 20.9-mW and achieves an RMS jitter of 6.2 ps, corresponding to a figure of merit (FOM) of −211-dB.