MOSFET modeling of 0.18μm CMOS technology at 4.2K using BP neural network. (February 2023)

• Record Type: Journal Article
• Authors: Wang, Qiuwei; Ye, Mao; Li, Yao; Zheng, Xiaoxiao; He, Jiaji; Du, Jun; Zhao, Yiqiang
• Is Part Of: Microelectronics journal. Volume 132(2023)
• Publication Date: 2023-02
• Subjects: Cryogenic CMOS -- LHT -- MOSFET modeling -- BP neural network -- Verilog-A; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105678
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Cryogenic CMOS circuits are widely applied to various fields, such as infrared focal plane arrays, space exploration, and quantum computing. The carrier freeze-out effect at cryogenic temperatures leads to abnormal changes in the characterization of the devices. These cause the performance degradation of circuits or even failure to work. As the industry-standard models provided by manufacturers of CMOS technology cannot describe the cryogenic effects, a complete and precise cryogenic model is required for circuit simulation at cryogenic temperatures. This paper presents the characterization of Semiconductor Manufacturing International Corporation (SMIC) 0 . 18 μ m CMOS technology at the liquid helium temperature (LHT). To solve the above problem, a metal–oxide–semiconductor field-effect transistor (MOSFET) modeling method at cryogenic temperatures using a back propagation (BP) neural network is proposed. The cryogenic model is first revised based on the BSIM model by extracting physical parameters. Then an optimization model predicted by BP neural network is proposed to calibrate the cryogenic effects. The cryo-model composed of the revised BSIM model and the optimization model can accurately describe the characteristics of MOSFETs with various aspect ratios under different bias voltages at 4.2K, which is not accessible for the standard BSIM model. Meanwhile, the optimization model based on BP neural network has been translated into Verilog-A language to be applied to the SPICE simulator successfully. Highlights: The cryogenic characterization of SMIC 0 . 18 μ m CMOS technology at 4.2K is presented. An optimization model VCCS is proposed to calibrate the cryogenic characteristics. BP neural network is, for the first time, used in MOSFET modeling. The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.