SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer. (February 2023) - Li, Qiang; Tao, Jun; Han, Jun
Abstract: In this study, we provide an automatic multi-objective optimization framework for RISC-V processor microarchitecture. CoreMark benchmark and TSMC 28 nm CMOS process serve as the foundation for SPARK's investigation of the design space to SonicBOOM for three design criteria of performance, power, and area. The sequential-BOED method demonstrates a convergence speed of ADRS 2.125 times faster than baseline thanks to the benefits of the suggested sampling algorithm RED. In the meantime, the SPARK framework's SPA-Gen infrastructure parallelizes querying the VLSI flow of elite trials. Therefore, under the same convergence target of ADRS as sequential-BOED, the overall running time of Para-BOED algorithm can be further improved by a factor of 1.29. The official Two-Wide BOOM achieves a commendable compromise between performance score, power consumption, and area cost. SPARK framework, however, finds an optimal microarchitecture design of BOOM with improved performance-cost ratio compared to official Two-Wide BOOM within fully acceptable searching time. Highlights: Algorithm Level: Our suggested RED algorithm for obtaining representative designs and edge designs greatly accelerate the convergence of Pareto front. With the help of SPA-Gen infrastructure, our Para-BOED algorithm can effectively reduce the overall running time compared with baseline. Framework Level: We present a fully automatic multi-objective DSE framework for processor microarchitecture. The BOOM processor serves as the experimental object to validate the workflow. Noteworthy is the discovery of an optimal design with best performance-cost gain. True commercial foundation: The experiment is built on the TSMC 28 nm CMOS process library, CoreMark benchmark, and industry-standard EDA tools. The experimental settings show that SPARK framework is more like a real-world application scenario.