Double-precision hardware accelerator for incompressible Navier–Stokes equations solver based on discontinuous Galerkin method. (February 2023) - Tomczak, Tadeusz; Księżyk, Mariusz; Hanke, Jacek; Kostur, Marek; Marek, Maciej
Abstract: We present the first known hardware accelerator for a complete solver based on the modal discontinuous Galerkin method (DGM) of full incompressible Navier–Stokes equations. The solver is designed for hexahedral finite elements and, at the current stage, the modal basis is limited to second-order polynomials giving 27 degrees of freedom per finite element. The solution algorithm employs the projection method for the treatment of the incompressibility constraint, but the Poisson pressure equation is replaced with a parabolic equation solved in pseudo-time. Our implementation requires about 1 0 5 floating-point operations (FLOP) for a single finite element per time step, and its arithmetic intensity is 1.8 FLOP/byte on average. We also designed the hardware based on a set of simple, simultaneously working microprogrammable computing units that contain only a floating-point arithmometer and a small memory. The design fits a medium-size field-programmable gate array (FPGA, we used Xilinx XCZU15EG) and, for all tested cases excluding one, achieves performance over 100 000 mesh elements per second (122 000 in peak) with a reasonable hardware utilisation: memory bandwidth between 8 and 9 GB/s (over 0.4 of the machine peak) and computational performance between 13 and 15 GFLOPS (almost 0.7 of the peak). The main reasons limiting hardware utilisation are: internal hardware limits in FPGA that prevent allocation of all DDR memory bandwidth for computations; and the differences in arithmetic intensities of different parts of the algorithm — the arithmetic intensities vary between 1.1 and 3.3 FLOP/byte. Highlights: The first hardware accelerator based on the modal discontinuous Galerkin method. Five parallel kernels with low memory traffic and balanced arithmetic intensities. Highly parallel hardware with simple computing units working simultaneously. Minimised hardware overheads by applying circuit for reindexing Gauss points. Detailed complexity estimations and performance analysis of the implementation.