A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment. (January 2023)

• Record Type: Journal Article
• Authors: Le, Anh-Tien; Hoang, Trong-Thuc; Dao, Ba-Anh; Tsukamoto, Akira; Suzaki, Kuniyasu; Pham, Cong-Kha
• Is Part Of: Computers & electrical engineering. Volume 105(2023)
• Publication Date: 2023-01
• Subjects: RISC-V -- Spectre -- Side-channel attack -- Trusted execution environment -- Cache memory -- Secure enclave -- Hybrid processor -- Open source -- Software -- Security; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2022.108546
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: The trust execution environment (TEE) provides a safe region, also known as a secret enclave, for executing private programs that need protection. This work proposed a cross-process exploitation scheme for conducting the cache side-channel attack, Spectre, on RISC-V processors with a trust execution environment. Practical experiments are provided to verify the protected enclave's security on RISC-V processors with the TEE. In these experiments, the attacker and victim do not share the same address space as in known implementations but are executed in separate processes. The experimental results show that initial leakage information from the cache memory can be recorded. To the best of our knowledge, no prior research has been conducted on the Spectre attack against RISC-V's TEE. This implementation will be a critical component for extending further cache side-channel experiments on the security of RISC-V processors. Graphical abstract: Highlights: Replicate cache side-channel attack variants on an FPGA with the RISC-V processor's configuration. Implement a cross-process side-channel attack via cache scenario for the first time on the RISC-V platform. Experiment with cache side-channel attacks on the RISC-V processor with trusted execution environment (TEE). Implement software countermeasures for RISC-V applications against Spectre attacks.