Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. (January 2023)

• Record Type: Journal Article
• Authors: Rathor, Mahendra; Anshul, Aditya; Bharath, K; Chaurasia, Rahul; Sengupta, Anirban
• Is Part Of: Computers & electrical engineering. Volume 105(2023)
• Publication Date: 2023-01
• Subjects: Reusable IP core -- HLS -- Watermarking -- Hardware security -- DSP; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2022.108476
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Reusable hardware intellectual property (IP) cores play a significant role in the modern system on chip (SoC) designs. However, raging threats of IP piracy and IP ownership infringement sabotage revenue and reputation of genuine IP vendors. This paper presents a novel quadruple phase watermarking for securing hardware IP cores during high level synthesis (HLS). The proposed approach introduces several novelties: graph partitioning, encoding tree, and eightfold mapping to generate a robust watermarking signature. Further, embedding signature during four phases of HLS viz . scheduling, register binding, resource binding and interconnect binding leads to a high-quality watermark. The proposed results indicate multiple times lower Pc and higher tamper tolerance than previous approaches, at negligible design cost overhead. We achieved improvements in Pc and tamper tolerance up to 10 18 and 10 52 times respectively than related works. Finally, security and design cost tradeoff for various signature strengths is presented.