Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters. Issue 1 (28th November 2022)

• Record Type: Journal Article
• Authors: Sadeghi, Ayoub; Shiri, Nabiollah; Rafiee, Mahmood; Darabi, Abdolreza; Abiri, Ebrahim
• Is Part Of: IET computers & digital techniques. Volume 17:Issue 1(2023)
• Page Start: 1
• Page End: 19
• Publication Date: 2022-11-28
• Subjects: CNTFET -- digital counter -- gate‐diffusion input (GDI) -- heat distribution -- voltage over‐scaling; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12049
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage ( V th ) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. Abstract : A new low‐power and high‐speed multiplier is presented based on voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. VOS technique is used to reduce power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier.