Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates. (18th August 2016)

• Record Type: Journal Article
• Authors: Nguyen, Phuong; Barraud, Sylvain; Cassé, Mikael; Pelloux-Prayer, Johan; Tabone, Claude; Hartmann, Jean-Michel; Arvet, Christian; Bernier, Nicolas; Hutin, Louis; Ecarnot, Ludovic; Maleville, Christophe; Nguyen, Bich-Yen; Mazure, Carlos; Faynot, Oliver; Vinet, Maud
• Is Part Of: ECS transactions. Volume 75:Number 8(2016)
• Page Start: 59
• Page End: 65
• Publication Date: 2016-08-18
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/07508.0059ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : We present for the first time the successful fabrication of Ω-gate P-type FETs with epitaxial compressively-strained SiGe (Ge=30%) on tensily-strained SOI substrates. The recess down to the strained-Si etch-stop layer in the source/drain (S/D) areas (after spacer etching) followed by a selective epitaxy of in-situ boron-doped Si0.7 Ge0.3 raised S/Ds allowed us to offset the performance loss due to tensile strain in short gate length Si0.7 Ge0.3 /sSi NW devices. The hole mobility improvement resulting from the compressive strain and VTH shift between Si0.7 Ge0.3 /sSi and Si channel transistors led to an ION current improvement of +100% at LG =15nm compared to SOI, providing a promising path for performant CMOS integration.