An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation. (4th March 2009) - Poikonen Poikonen, Jonne Jonne; Laiho Laiho, Mika Mika; Paasio Paasio, Ari Ari; Koskinen Koskinen, Lauri Lauri; Halonen Halonen, Kari Kari
Abstract : A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8, 8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μ m CMOS technology.