Development of a timing chip prototype in 110 nm CMOS technology. Issue 1 (1st November 2022) - Caminada, L; Kilminster, B; Macchiolo, A; Meier, B; Senger, M; Wiederkehr, S
Abstract : We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of 100x100 μm 2, where the sensors are Low Gain Avalanche Diodes (LGADs). The long term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the High Luminosity LHC (HL-LHC). The requirements for this ASIC are the incorporation of a Time to Digital Converter (TDC) in the small pixel area, low power consumption, and radiation tolerance up to 5 × 10 15 n eq cm −2 to withstand the radiation levels in the innermost detector modules for 3000 fb −1 of the HL-LHC (in the TEPX). A prototype has been designed and produced in 110 nm CMOS technology at LFoundry and UMC with different versions of TDC structures, together with a front end circuitry to interface with the sensors. The design of the TDC will be discussed, with the test set-up for the measurements, and the first results comparing the performance of the different structures.