Generation of logic designs for efficiently solving ordinary differential equations on field programmable gate arrays. (19th October 2021)

• Record Type: Journal Article
• Authors: Bartel, Silas; Korch, Matthias
• Other Names: Chandrasekaran Sunita guestEditor.; Si Min guestEditor.; Zhai Jidong guestEditor.; Oden Lena guestEditor.
• Is Part Of: Software, practice & experience. Volume 53:Number 1(2023)
• Page Start: 27
• Page End: 52
• Publication Date: 2021-10-19
• Subjects: code generation -- FPGA -- hardware accelerators -- ODE -- reconfigurable architectures -- Runge–Kutta method; Computer software -- Periodicals; Computer programming -- Periodicals; Computer programs -- Periodicals; 005.3
• DOI: 10.1002/spe.3043
• Languages: English
• ISSNs: 0038-0644

Abstract

Abstract: Ordinary differential equations can be used to describe simulation models. As such, solving these equations is an important task in the high performance computing (HPC) domain. Field programmable gate arrays (FPGAs) are a promising platform, expected to be usable as efficient accelerators for such computations. While the use of hardware description languages (HDLs) can produce very efficient logic designs, their unique concept is hard to adopt for scientists and software engineers. High‐level synthesis (HLS) tools promise faster development, but bear the risk of lower performance and increased resource consumption of the final design. But even when using HLS tools the user still requires specialized knowledge about FPGAs and circuit design. In order to reach a wide adoption of FPGAs in HPC applications, a need for simple to use tools which enable performant designs was identified. This article proposes a framework that is able to automatically generate specific and optimized solver logic from easy to handle configuration files. No manual development, nor special FPGA or programming knowledge is required. To measure the capability of the proposed tool, the performance was evaluated for different solver methods and compared with an alternative hand optimized HLS implementation. The logic generated by this improved approach is up to 43 times faster than its hand optimized HLS counterpart, depending on the solution method.