Combining reduction with synchronization barrier on multi‐core processors. (1st December 2022)

• Record Type: Journal Article
• Authors: Mohamed El Maarouf, Aboul‐Karim; Giraud, Luc; Guermouche, Abdou; Guignon, Thomas
• Is Part Of: Concurrency and computation. Volume 35:Number 1(2023)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-12-01
• Subjects: barrier -- butterfly barrier -- reduction -- shared memory -- SIMD -- synchronization primitives; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.7402
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: With the rise of multi‐core processors with a large number of cores, the need for shared memory reduction that performs efficiently on a large number of cores is more pressing. Efficient shared memory reduction on these multi‐core processors will help share memory programs be more efficient. In this article, we propose a reduction method combined with a barrier method that uses SIMD read/write instructions to combine barrier signaling and reduction value to minimize memory/cache traffic between cores, thereby reducing barrier latency. We compare different barriers and reduction methods on three multi‐core processors and show that the proposed combining barrier/reduction methods are 4 and 3.5 times faster than respectively GCC 11.1 and Intel 21.2 OpenMP 4.5 reduction.