2D Materials‐Based Static Random‐Access Memory. Issue 48 (21st January 2022)

• Record Type: Journal Article
• Authors: Liu, Chang‐Ju; Wan, Yi; Li, Lain‐Jong; Lin, Chih‐Pin; Hou, Tuo‐Hung; Huang, Zi‐Yuan; Hu, Vita Pi‐Ho
• Is Part Of: Advanced materials. Volume 34:Issue 48(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-01-21
• Subjects: 2D materials -- complementary metal‐oxide‐semiconductors -- field‐effect transistors -- high performance -- static random‐access memory; Materials -- Periodicals; Chemical vapor deposition -- Periodicals; 620.11
• DOI: 10.1002/adma.202107894
• Languages: English
• ISSNs: 0935-9648

Abstract

Abstract: 2D transition‐metal dichalcogenide semiconductors, such as MoS2 and WSe2, with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)‐based field‐effect transistor (FET) and static random‐access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read–write conflict in an SRAM cell at scaled technology nodes (1–2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state‐of‐the‐art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1‐nm node. Applying the nanosheet (NS) gate‐all‐around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost‐effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed. Abstract : The optimized two‐dimensional material (2DM) static random‐access memory designed with state‐of‐the‐art contact resistance leads to excellent stability and operation speed at the 1‐nm node. Applying the nanosheet gate‐all‐around structure to 2DMs further improves speed and area density, showing the feasible scaling path beyond the Si technology. The process challenges of 2DM nanosheet field‐effect transistors are also discussed.