Low clock skew superconductor adiabatic quantum-flux-parametron logic circuits based on grid-distributed blocks. (1st January 2023)

• Record Type: Journal Article
• Authors: He, Yuxing; Ayala, Christopher L; Zeng, Yu; Zou, Xihua; Yan, Lianshan; Pan, Wei; Yoshikawa, Nobuyuki
• Is Part Of: Superconductor science & technology. Volume 36:Number 1(2023)
• Publication Date: 2023-01-01
• Subjects: adiabatic quantum-flux-parametron (AQFP) -- superconductor logic -- microwave H-tree -- low clock skew; Superconductivity -- Periodicals; Superconductors -- Periodicals; 537.623
• DOI: 10.1088/1361-6668/aca3d6
• Languages: English
• ISSNs: 0953-2048

Abstract

Abstract: Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several levels of TLs by using passive splitters, creating multiple leaves at the final level. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising four blocks with data interconnections between each other, and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.