A multi‐variable double impedance matching network design algorithm with design example of a low noise amplifier. Issue 12 (11th October 2022)

• Record Type: Journal Article
• Authors: Bajpai, Neha; Chauhan, Yogesh Singh
• Is Part Of: International journal of RF and microwave computer-aided engineering. Volume 32:Issue 12(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2022-10-11
• Subjects: broadband matching network -- EMI/EMC -- GaAs -- HEMT -- impedance line‐segmentation algorithm -- load‐pull -- low noise power amplifier -- MMIC -- RF/microwave -- synthesis; Microwave devices -- Computer-aided design -- Periodicals; Computer-aided engineering -- Periodicals; 621.3813
• DOI: 10.1002/mmce.23462
• Languages: English
• ISSNs: 1096-4290

Abstract

Abstract: In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x and frequency ω, respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n linear segments, represented by the weighted sum of n semi‐infinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3–2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm 2 of chip area.