A comparative study on performance of junctionless Bulk SiGe and Si FinFET. (December 2022)

• Record Type: Journal Article
• Authors: Shi, Xinlong; Hu, Huiyong; Wang, Ying; Wang, Liming; Zhang, Ningning; Wang, Bin; Yang, Maolong; Meng, Lingyao
• Is Part Of: Microelectronics journal. Volume 130(2022)
• Publication Date: 2022-12
• Subjects: Junctionless -- Bulk FinFET -- SiGe -- CMOS inverter; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105537
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, the n-type and p-type SiGe junctionless bulk FinFET (SiGe JL-FinFET) with a high Ge mole fraction (xF>0.8) was studied for characteristics of a single device and the CMOS logic circuit using 3D numerical simulation. A comparison study between SiGe JL-FinFET and Si JL-FinFET under 1 × 1 0 19 to 5 × 1 0 19 doping concentrations. The SiGe JL-FinFET exhibits a 28% and 9% enhancement of hole and electron mobility, thus the saturation current, transconductance, intrinsic gain, and intrinsic delay are improved up to 38%, 26%, 45% and 27% in the SiGe-based device as compared to the Si-based device. Due to the higher mobility and lower gate capacitance of SiGe JL-FinFET, the rise time, fall time, propagation delay, and maximum operating frequency of the CMOS inverter are also improved up to 34%, 13%, 9%, and 20%, respectively, compared to their Si-based counterparts. This SiGe junctionless device has a simple fabrication process and improvements in analog and digital performance at the sub-5 nm technology node, making this device a promising architecture for high-performance CMOS logic applications. Highlights: At the sub-5 nm node, the n- and p-type SiGe JL-FinFET with a high Ge mole fraction was studied on the device characteristics and the CMOS logic performance. The I o n, G m, A v, and τ D are improved up to 38%, 26%, 45% and 27% in the SiGe device as compared to the Si device. The T r, T f, T d, and f m of the CMOS inverter are improved up to 34%, 13%, 9%, and 20%, respectively, compared to their Si counterparts.