A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique. (December 2022)

• Record Type: Journal Article
• Authors: Zhang, Chenghao; Wei, Jiangbo; Yang, Yihang; Liu, Maliang
• Is Part Of: Microelectronics journal. Volume 130(2022)
• Publication Date: 2022-12
• Subjects: Analog-to-digital converter (ADC) -- Pipelined -- Residue amplifier -- Left half plane (LHP) -- High resolution -- Comparator; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105611
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper describes a 12-bit 1.25-GS/s RF sampling pipelined analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. To achieve high-speed and high-resolution conversion, a two-stage push-pull residue amplifier powered by a dual-supply is employed. A left half-plane (LHP) zero is generated through the coupling capacitance to expand the bandwidth and an inverter-based auxiliary amplifier is used to improve the gain and simplify the design. In addition, the proposed residue amplifier achieves a stable closed-loop characteristic without adding compensation capacitance, which greatly saves the area and improves the power efficiency. With an 18 MHz and 2 Vpp input signal, the SNDR is 61.5 dB, the SFDR is 70.2 dB. And the SNDR and SFDR are greater than 58 dB and 69 dB over the entire Nyquist bandwidth while the power consumption is 45.6 mW.