P‐11: Effects of Ar Dilution on N2O/SiH4 PECVD for the Growth of Silicon Oxide Thin Films with Improved Breakdown Voltage Characteristics. Issue 1 (28th June 2022)

• Record Type: Journal Article
• Authors: Kim, Aram; Lee, Bokyoung; Kim, Hyeona; Bang, Jungho; Nam, Seung Hee; Park, Kwon-Shik; Kim, Jeomjae; Yoon, Soo Young
• Is Part Of: Digest of technical papers. Volume 53:Issue 1(2022)
• Page Start: 1078
• Page End: 1080
• Publication Date: 2022-06-28
• Subjects: Gate dielectric -- Silicon oxide -- PECVD -- Breakdown voltage -- Film uniformity -- LTPS TFT -- N2O-SiH4 plasma; Information display systems -- Congresses; 621.3815422
• DOI: 10.1002/sdtp.15686
• Languages: English
• ISSNs: 0097-966X

Abstract

Abstract : In order to obtain a robust gate dielectric, the nitrogen atom incorporation in the silicon oxide thin film has been investigated in much prior study in recent years. Silicon oxide thin film deposition is mainly performed using SiH4 ‐N2 O plasma by the Plasma enhanced chemical vapor deposition (PECVD) system. Reducing the N2 O/SiH4 gas flow ratio increases the nitrogen content in the film. However, the film uniformity dramatically deteriorates as the N2 O/SiH4 ratio is decreased and this issue makes the low N2O/SiH4 ratio condition a challenging area for the process condition. In this study, to overcome this problem Argon (Ar) addition was employed to the low N2O/SiH4 ratio plasma and we found that Ar not only allows the thin film to be uniformly deposited by increasing the plasma density due to the penning effect, but also increases Si‐N bond especially under the ratio of 10:1 condition. Even though the silicon oxide thin film was deposited with low N2O/SiH4 gas flow rate, the film uniformity and breakdown voltage characteristics dramatically improved by Ar dilution. In addition, LTPS p‐channel TFT was fabricated by utilizing the improved silicon oxide thin film as a gate dielectric layer and it showed excellent electrical characteristics. This work would be one of the most practical solutions for robust gate dielectric deposition.