A hybrid five‐level inverter configuration with improved reliability and reduced number of components. (20th July 2022)

• Record Type: Journal Article
• Authors: Saketi, Sai Krishna; Chaturvedi, Pradyumn; Yadeo, Dharmendra; Atkar, Dipesh
• Is Part Of: International journal of circuit theory and applications. Volume 50:Number 11(2022)
• Page Start: 4104
• Page End: 4130
• Publication Date: 2022-07-20
• Subjects: capacitor voltage balancing -- fault‐tolerant multilevel inverter -- flying capacitor leg -- reduced carrier based level shifted sinusoidal pulse width modulation -- reliability; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3376
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: The provision of significant redundant states in multilevel inverters (MLIs) aids in fault‐tolerant operation. However, this deals with several components, leading to low reliability. This paper proposes a new fault‐tolerant five‐level MLI with reduced component count, which can withstand both single‐ and multiple‐switch faults. The reduced carrier‐based level shifted sinusoidal pulse width modulation (RCLSPWM) strategy is developed to generate control signals for the switches. The employed control scheme automatically balances the voltage across the capacitor. The logic gate expressions for generating gate pulses of the switches under normal and fault‐tolerant operating modes are described in detail. The comparative analysis is carried out to demonstrate the effectiveness of the proposed topology over other existing similar topologies. The performance of the laboratory prototype developed is found satisfactory as compared to other existing topologies under various operating conditions. Abstract : This paper proposes a new fault‐tolerant five‐level MLI with reduced component count, which can withstand both single‐ and multiple‐switch faults. The comparative analysis is carried out to demonstrate the effectiveness of the proposed topology over other existing similar topologies. The performance of the laboratory prototype developed is found satisfactory as compared to other existing topologies under various operating conditions.