Analytical model and simulation‐based analysis of a work function engineered triple metal tunnel field‐effect transistor device showing excellent device performance. Issue 1 (13th December 2020)

• Record Type: Journal Article
• Authors: Bose, Ria; Roy, Jatindra Nath
• Is Part Of: IET circuits, devices & systems. Volume 15:Issue 1(2021)
• Page Start: 11
• Page End: 19
• Publication Date: 2020-12-13
• Subjects: Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/cds2.12009
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract: In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field‐effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation‐based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n + pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n ‐pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10 −4 S/μm), low energy‐delay product (24.601 fJ‐ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.